Traditionally, serial digital audio decoders have used a PLL to lock to the incoming signal. However, in order to use a PLL in a serial digital audio decoder, various external components are typically required. As a result, serial digital audio decoders which incorporate a PLL tend to be both expensive and unwieldy. Furthermore, PLLs cannot readily be switched between manufacturing technologies. As a result, PLLs are not particularly well suited for use in devices which integrate plural design technologies, for example, different FPGA families and/or different standard cell and gate array families.